Job?Summary
As?a?member?of?the?core?backend?team,?you?will?be?responsible?for?the?physical?implementation?(from?netlist?to?tapeout)?of?a?highly?complex?SOC?utilizing?state?of?the?art?process?technology.
Description
??Work?with?FE?team?to?understand?chip?architecture?and?drive?physical?aspects?early?in?design?cycle.
??Design?automation;?Construct,?Guide,?Modify,?Enhance?Timing?tools?and?flows.
??Top?level?floorplan,?partition?floorpan,?P&R,?timing?and?physical?sign?off.
Key?Qualification
??The?ideal?candidate?will?have?a?minimum?of?3?years?of?physical?design?experience,?with?recent?successful?tapeouts?in?deep?sub-micron?technology.
??Expert?in?top?/block?level?P&R?implementation,?including?floorplanning,?clock?&?power?distribution,?timing?closure,?physical?&?electrical?verification.
??Experienced?in?industry?standard?tools,?understand?their?capabilities?and?underlying?algorithms.
??Strong?communication?skills.
??Familiar?with?sub-micro?Synthesis,?PR?and?power?sign?off?tool?is?a?plus.
??Experience?with?DDR,?PCIE?is?a?plus.
??Strong?scripting?abilities?in?Python?are?needed;?TCL?or?Makefile?is?a?plus.
??Experience?in?methodology?of?Technology?under?16nm?is?a?plus.
??Experience?in?large?-?scale?chip?design?is?a?plus.
Education
BS/MS?CE?or?EE.
