Description?
?o?Work?with?FE?team?to?understand?design?architecture?and?drive?physical?aspects?early?in?design?cycle.?
?o?Design?automation;?Construct,?Guide,?Modify,?Enhance?PNR/TEMPUS/VOLTUS?flows.?
?o?Top/Block?level?floorplan,?P&R,?timing?and?physical?sign?off.?
?Key?Qualification?
?o?The?ideal?candidate?will?have?a?minimum?of?3?years?of?physical?design?experience,?with?recent?successful?tapeout?in?deep?sub-micron?technology.?
?o?Has?experience?in?top?/block?level?P&R?implementation,?including?floorplanning,?clock?&?power?distribution,?timing?closure,?physical?&?electrical?verification.?
?o?Experienced?in?industry?standard?tools,?understand?their?capabilities?and?underlying?algorithms.?
?o?Strong?communication?skills.?
?o?Familiar?with?sub-micro?Synthesis,?PR?and?power?sign?off?tool?is?a?plus.?
?o?Experience?with?DDR,?PCIE?is?a?plus.?o?Strong?scripting?abilities?in?Python?are?needed;?TCL?or?Makefile?is?a?plus.?
?o?Experience?in?methodology?of?Technology?under?16nm?is?a?plus.?
?o?Experience?in?large?-?scale?chip?design?is?a?plus.
